[OT] Forcing 64-bit PCI Transactions

Does anyone know what governs a 64-bit PCI transaction being executed vs. a
32-bit one? We have some anecdotal information about an Itanium motherboard
that would only start doing 64-bit transactions when the PCI bridge
(Northbridge) FIFO reached a certain point. This despite the processor
doing 64-bit transactions on it's local bus. And yes, the PCI bus was a
64-bit bus. These folks had a custom 64-bit card that was also a bus
master. When their card took control of the bus, the transactions were all
64-bit and the processor handled them accordingly.

Is the PCI transaction size governed by the OS (settings or device driver)?
Hardware setup (presumably via the BIOS)? Or is it governed (and limited)
by the functionality of the PCI bridge hardware.

Any ideas, pointers to references, comments, etc will be greatly
appreciated!

Thanks!!

Don

According to the spec, this is governed only by abilities of 2 devices, and
2 64bit devices MUST use 64bit transactions.

--
Maxim Shatskih, Windows DDK MVP
StorageCraft Corporation

http://www.storagecraft.com


"Don" <> wrote in message
news:...
> Does anyone know what governs a 64-bit PCI transaction being executed vs. a
> 32-bit one? We have some anecdotal information about an Itanium motherboard
> that would only start doing 64-bit transactions when the PCI bridge
> (Northbridge) FIFO reached a certain point. This despite the processor
> doing 64-bit transactions on it's local bus. And yes, the PCI bus was a
> 64-bit bus. These folks had a custom 64-bit card that was also a bus
> master. When their card took control of the bus, the transactions were all
> 64-bit and the processor handled them accordingly.
>
> Is the PCI transaction size governed by the OS (settings or device driver)?
> Hardware setup (presumably via the BIOS)? Or is it governed (and limited)
> by the functionality of the PCI bridge hardware.
>
> Any ideas, pointers to references, comments, etc will be greatly
> appreciated!
>
> Thanks!!
>
> Don
>
>
>
>