PCIe Driver read problem

So from the processor issuing the read request to PCIe, and the device
sending the completion to the processor, it might take 400-600-900 ns? No
surprise you're getting only 4MB/s. This is even slower than 33 MHz 32 bit
PCI.

"Charles Gardiner" <> wrote in message
news:he9nr2$rf$00$...
> Alexander Grigoriev schrieb:
>
>>
>> Do you mean 600-900 ns is your FPGA's roundtrip time? Do you have PCIe
>> analyser? It would come very handy to debus such issues.
>>
>>
> The figures are:
> - roughly 450 ns for the first few packets, i.e. buffers empty plenty of
> credits
> - typical 600 ns, DMA traffic but no credit stalls
> - worst 900 ns, heavy DMA and some credit stalls
>
> With the round-trip time, I mean first header DWORD into PCIe core in
> requestor to last DWORD of completion packet arriving at requestor. This
> was measured in simulation with two identical PCIe cores connected
> back-to-back (Aldec VHDL/Verilog simulator, Lattice ECP2M FPGA). i.e.
> this is the time that user logic in the PCIe end-point would see if the
> completer was a pure hardware implementation and could deliver data as
> soon as the request had been received.
>
> Packet transmission is normally pretty fast. It's the reception that's
> slow since the packet has to be checked by the data-link layer before
> passing it on to the user/application logic. Switches in the path often
> use transparent mode i.e. the data layer checks on the fly and issues a
> 'nullify' if it unexpectedly detects a link CRC error.
>
> The assumption here is of course that all chips have much the same
> overhead in the data-link/physical layers. From the figures I have from
> different chips or heard from people on different projects, this is the
> case. In PCIe Gen 1.x, your byte time is 4 ns (UI 400 ps).

Thank for all you guys.
I have learned a lot from your disscussion, since I'm a rookie in windows
driver development.
My project is mostly like Charles says, except that the FPGA only attatched
DDR RAM without a DMA adapter.
Do you guys means that it is no possible to accelerate the read speed
withourt DMA involved?
Do I have to persuade the hardware designer to add a DMA adapter on the
board?or the FPGA can implement the function of a DMA adapter?

--
shingo for windows driving & winCE driving


"Alexander Grigoriev" wrote:

> So from the processor issuing the read request to PCIe, and the device
> sending the completion to the processor, it might take 400-600-900 ns? No
> surprise you're getting only 4MB/s. This is even slower than 33 MHz 32 bit
> PCI.
>
> "Charles Gardiner" <> wrote in message
> news:he9nr2$rf$00$...
> > Alexander Grigoriev schrieb:
> >
> >>
> >> Do you mean 600-900 ns is your FPGA's roundtrip time? Do you have PCIe
> >> analyser? It would come very handy to debus such issues.
> >>
> >>
> > The figures are:
> > - roughly 450 ns for the first few packets, i.e. buffers empty plenty of
> > credits
> > - typical 600 ns, DMA traffic but no credit stalls
> > - worst 900 ns, heavy DMA and some credit stalls
> >
> > With the round-trip time, I mean first header DWORD into PCIe core in
> > requestor to last DWORD of completion packet arriving at requestor. This
> > was measured in simulation with two identical PCIe cores connected
> > back-to-back (Aldec VHDL/Verilog simulator, Lattice ECP2M FPGA). i.e.
> > this is the time that user logic in the PCIe end-point would see if the
> > completer was a pure hardware implementation and could deliver data as
> > soon as the request had been received.
> >
> > Packet transmission is normally pretty fast. It's the reception that's
> > slow since the packet has to be checked by the data-link layer before
> > passing it on to the user/application logic. Switches in the path often
> > use transparent mode i.e. the data layer checks on the fly and issues a
> > 'nullify' if it unexpectedly detects a link CRC error.
> >
> > The assumption here is of course that all chips have much the same
> > overhead in the data-link/physical layers. From the figures I have from
> > different chips or heard from people on different projects, this is the
> > case. In PCIe Gen 1.x, your byte time is 4 ns (UI 400 ps).
>
>
> .
>

shingo schrieb:

> Do you guys means that it is no possible to accelerate the read speed
> withourt DMA involved?

Yes, unfortunately you will not get any decent transfer rates without DMA.

> Do I have to persuade the hardware designer to add a DMA adapter on the
> board?or the FPGA can implement the function of a DMA adapter?
>
I'd put the DMA controller in the FPGA.
I'm sure nearly every FPGA manufacturer has some DMA controller in his
IP-library, some are probably even free. It's not the most complicated
piece of logic to do yourself either. Essentially, your driver must feed
the DMA controller with the scatter/gather lists describing your IRP
buffer. The PciDrv and PLX9xxx examples in the WDK are great for getting
started.

Thanks
I will add DMA function in my FPGA as soon as possible.
It is glad to learn so much things from you guys.
I appreciate all your help sincerely.
--
shingo for windows driving & winCE driving