You have a work email but are unemployed! That is a good one.
Camper
"Stan Starinski" <China@stealsUSJobsPatentsSoftwareMusicVideo> wrote in
message news:...
> I've exchanged emails w/Microchp SMTD-division Vice President & believe
> posting his through, excellent response would benefit all.
> Here's his response received at my work email. Nothing confidential here
> so may post:
> =========
>
> From Steve Drehoble <>
> CC: Mitch Little <> <--that's another "big gun"
> @MCP, I never wrote to him, he gets copied anyway.
>
> Mr. S*****,
>
> Hello and thanks for taking the time to provide us your thoughts and
> feedback.
> Thanks for letting me take a few days to think about your comment and
> review it with my people. It's a tough problem.
> As you know, the overall trends from our customers are smaller & smaller
> for size and weight. The weight is not an issue for the
> The Package difference it self, but for the overall cumulative PC board
> area in shipping and Mfg costs.
>
> The other areas for smaller size are in EMC and leakage currents
> (especially at cold temperatures). As semiconductor transistor channel
> lengths get smaller, the ability for the silicon to absorb a noise event
> goes down, hence the shorter leads. The leakage current is very important
> for low power design practices - even for applications plugged into a
> wall. As the silicon power goes down, the external leakage paths become
> vital, especially on pins like a low power osc. The solder paths can have
> leakage higher than the internal silicon paths. It is all getting smaller
> and smaller. Unfortunately, Socketing complicates all of these issues.
>
> There is not a good silicon or packaging answer to the socketing dilemma
> when dealing with an application is dealing with the above issues.
> Probably 90-95% of our customers' applications fall into one of these SMT
> apps. Customers are also very concerned about cost. An SSOP and SOIC is
> becoming cheaper to produce on a new products than a PDIP or PLCC. We
> understand this is an issue for system designers. This is one of the
> reasons why we offer extensive training at our MASTSERs and RTC programs
> to address these system design issues. We still do see people performing
> the basic prototypes with a PDIP - IF AND WHEN ABLE !!, then moving to SMT
> for final verification. We see little to zero interest so far in a PLCC
> for early prototyping. On many of our new 8 bit products, we still offer
> PDIP as an option. Many of our competitors have dropped this offering.
>
> Also, we now see QFN packages becoming a preferred package as well, which
> I sympathize with you it, it is a much more difficult package to prototype
> in. The next step we are seeing emerging in high volume apps are in Chip
> Scale Packaging (CSP) . This is even tighter than a QFN. It is the
> ultimate small "packageless" package. You can contact your local MCHP
> office for support and training class schedules in the design techniques.
>
> Hope this helps,
>
> Steve Drehobl
> Vice President , SMTD Division
> Microchip Technology
|
Similar Threads
Linear Mode
