PCI-E Vendor Defined Messages

Discussion in 'Windows Vista Drivers' started by Colin Hankins, Dec 22, 2007.

  1. Does Windows support PCI Express Vendor Defined Messages? If so, what is the
    mechanism for sending vendor defined messages in the ddk?
     
    Colin Hankins, Dec 22, 2007
    #1
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  2. Colin Hankins

    Tim Roberts Guest

    "Colin Hankins" <> wrote:
    >
    >Does Windows support PCI Express Vendor Defined Messages? If so, what is the
    >mechanism for sending vendor defined messages in the ddk?


    No. Vendor-defined messages are a more-or-less useless part of the spec,
    designed for things like bus extenders where the two ends need to
    communicate with each other.

    There's really no problem you can't solve using normal cycles.
    --
    Tim Roberts,
    Providenza & Boekelheide, Inc.
     
    Tim Roberts, Dec 23, 2007
    #2
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  3. That is disappointing. I thought it would come in usefull, from the host
    system point of view, to send one message simultaneously (since the Vendor
    Defined Messages allows for broadcast type routing) from the the host to
    multiple cards in the PCI-E fabric. Yes, I can accomplish the same thing
    with individual writes to each board, but one message would have been much
    cooler and less bandwidth.

    Thanks for the reply.

    "Tim Roberts" <> wrote in message
    news:...
    > "Colin Hankins" <> wrote:
    >>
    >>Does Windows support PCI Express Vendor Defined Messages? If so, what is
    >>the
    >>mechanism for sending vendor defined messages in the ddk?

    >
    > No. Vendor-defined messages are a more-or-less useless part of the spec,
    > designed for things like bus extenders where the two ends need to
    > communicate with each other.
    >
    > There's really no problem you can't solve using normal cycles.
    > --
    > Tim Roberts,
    > Providenza & Boekelheide, Inc.
     
    Colin Hankins, Dec 24, 2007
    #3
  4. Colin Hankins

    Tim Roberts Guest

    "Colin Hankins" <> wrote:
    >
    >That is disappointing. I thought it would come in usefull, from the host
    >system point of view, to send one message simultaneously (since the Vendor
    >Defined Messages allows for broadcast type routing) from the the host to
    >multiple cards in the PCI-E fabric. Yes, I can accomplish the same thing
    >with individual writes to each board, but one message would have been much
    >cooler and less bandwidth.


    It's more complicated than that. Remember that the processor doesn't
    really speak PCIExpress directly. There is a translation, in the south
    bridge. To do anything other than PCI-type transactions, you have to talk
    directly to the root complex. There are multiple roots in the typical PC,
    and there's no standard method for addressing them, so whatever you did
    would only work on a few architectures.

    The sad fact is that anything in PCIExpress that is not PCI-compatible is
    never going to get widespread adoption. That includes isochronous and
    virtual channels.
    --
    Tim Roberts,
    Providenza & Boekelheide, Inc.
     
    Tim Roberts, Dec 25, 2007
    #4
  5. If I recall correctly, some of the Intel north bridge to south bridge
    connections are very PCI-E like. In that they do have Vendor Defined
    Messaging and Virtual Channels to support QOS and Isochronous transfers. I
    assumed they would also extend this out the the actual PCI-E ports. Oh well.

    Would you happen to know of any "high-end" systems that incorpoate root
    complex chipsets that support full PCI-E specification (if there is such a
    device)?

    Again, thanks for the replies.

    "Tim Roberts" <> wrote in message
    news:...
    > "Colin Hankins" <> wrote:
    >>
    >>That is disappointing. I thought it would come in usefull, from the host
    >>system point of view, to send one message simultaneously (since the Vendor
    >>Defined Messages allows for broadcast type routing) from the the host to
    >>multiple cards in the PCI-E fabric. Yes, I can accomplish the same thing
    >>with individual writes to each board, but one message would have been much
    >>cooler and less bandwidth.

    >
    > It's more complicated than that. Remember that the processor doesn't
    > really speak PCIExpress directly. There is a translation, in the south
    > bridge. To do anything other than PCI-type transactions, you have to talk
    > directly to the root complex. There are multiple roots in the typical PC,
    > and there's no standard method for addressing them, so whatever you did
    > would only work on a few architectures.
    >
    > The sad fact is that anything in PCIExpress that is not PCI-compatible is
    > never going to get widespread adoption. That includes isochronous and
    > virtual channels.
    > --
    > Tim Roberts,
    > Providenza & Boekelheide, Inc.
     
    Colin Hankins, Dec 26, 2007
    #5
  6. Colin Hankins

    Tim Roberts Guest

    "Colin Hankins" <> wrote:
    >
    >If I recall correctly, some of the Intel north bridge to south bridge
    >connections are very PCI-E like. In that they do have Vendor Defined
    >Messaging and Virtual Channels to support QOS and Isochronous transfers. I
    >assumed they would also extend this out the the actual PCI-E ports. Oh well.
    >
    >Would you happen to know of any "high-end" systems that incorpoate root
    >complex chipsets that support full PCI-E specification (if there is such a
    >device)?


    There aren't very many chipset makers. It shouldn't be too hard to check
    them.

    However, again I ask: what's the point? Your code is only going to work on
    that chipset, and possibly even one version of that chipset. And, in the
    end, you're talking about an utter micro-optimization. You're going to
    invest days of effort in chasing down the mechanism and the possible
    applicable chipsets, for the sake of saving a handful of nanoseconds.

    It just doesn't make sense to me.
    --
    Tim Roberts,
    Providenza & Boekelheide, Inc.
     
    Tim Roberts, Dec 27, 2007
    #6
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